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Nvidia asks SK hynix to raise delivery timeline for next-gen HBM4 memory Chips are six months late, according to SK Group President Chey Tae-won Reuters.

Originally, SK hynix planned to ship HBM4 chips to customers in the second half of 2025. At the request of Nvidia CEO Jensen Huang, the timeline was shortened, although the exact new schedule was not specified. Nvidia is currently working on its next-generation GPUs that will use HBM4 memory for AI and HPC (possibly codename Rubin). For this reason, the company needs to get its hands on the next generation high-bandwidth memory as soon as possible.

SK hynix continues to consolidate its leadership in the HBM market, driven by increasing demand from the artificial intelligence industry. The company has supplied 8-Hi and 12-Hi HBM3E to Nvidia for the company’s current-generation products, and going forward, SK hynix plans to launch 12-layer HBM4 next year and aims to launch a 16-layer version by 2026. with anticipated industry needs.

Initially, SK Hynix was leaning towards using 1b DRAM technology for its HBM4 layers, but Samsung’s preference for the more advanced 1c manufacturing technology caused SK hynix to re-evaluate its approach.

The upcoming HBM4 standard will offer memory tiers of 24Gb and 32Gb, as well as stacking options consisting of 4-high, 8-high, 12-high, and 16-high TSV stacks. The exact configurations of the early HBM4 modules are still unclear; Samsung and SK hynix plan to start mass production of 12-high HBM4 stacks in the second half of 2025. The speedboxes of these modules will vary depending on many factors, but JEDEC’s preliminary standards set speeds up to 6.4 GT/s.

SK hynix is ​​partnering with TSMC to produce base molds for HBM4 modules. TSMC announced at the 2024 European Technology Symposium that it will produce these basic dies using 12FFC + (12nm class) and N5 (5nm class) process technologies. The N5 process will enable higher logic density and thinner interconnect spacings, allowing memory to be integrated directly into CPUs and GPUs. Alternatively, the 12FFC+ process would provide a more cost-effective solution, striking a balance between performance and affordability by using silicon intermediaries to connect memory to host processors.